1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having different synchronizing timings depending on a column address strobe (CAS) latency (hereinafter, referred to as a CL).
2. Description of the Related Art
As the operating frequency of a semiconductor memory system gradually increases, the performance of a semiconductor memory increases. Semiconductor memories are developed to have high frequency bandwidths. Synchronous DRAMs (SDRAMs) are synchronous semiconductor memories manufactured using a pipelining technique. SDRAMs are classified as single data rate (SDR) SDRAMs or double data rate (DDR) SDRAMs. An SDR SDRAM controls an output data buffer to be enabled/disabled in synchronization with the rising edge of every clock, that is, in synchronization with every clock cycle. A DDR SDRAM controls an output data buffer to be enabled/disabled in synchronization with every rising edge and every falling edge of a clock, that is, in synchronization with every half a clock cycle.
Hence, in an SDR SDRAM, a column address strobe (CAS) latency (hereinafter, referred to as a CL), which represents the reaction interval between the time when a column address is input to the memory until the time when data is output from the memory, must vary in units of one clock cycle, such as, CL=1, CL=2, CL=3, and the like. On the other hand, in a DDR SDRAM, the CL must vary in units of half a clock cycle, such as, CL=2, CL=2.5, CL=3, and the like. Accordingly, a DDR SDRAM requires a higher frequency bandwidth and a greater timing margin than those required by an SDR SDRAM.
FIG. 1 is a timing diagram of signals when data is read from a conventional DDR SDRAM. Referring to FIG. 1, outputting of data from the memory cells of a page selected by a row active operation is based on a column selection line signal CSL. The column selection line signal CSL is produced once during a cycle of an external clock signal EXTCLK. When a data read command READ is received after an external active command ACTIVE, the column selection line signal CSL is produced in synchronization with a rising edge of the external clock signal EXTCLK. When the CL is 2, data is read out in synchronization with a rising edge of the external clock signal EXTCLK that is two clock cycles after the data read command READ has been input. When the CL is 2.5, data is read out in synchronization with a falling edge of the external clock signal EXTCLK that is 2.5 cycles after the data read command READ has been received. When the CL is 3, data is read out in synchronization with a rising edge of the external clock signal EXTCLK that is three cycles after the data read command READ has been received.
Time between the timing of a rising edge of the external clock signal EXTCLK at which the data read command READ is received and the timing of readout of first data DQ0 is referred to as tAA. Also, tRCD (where RCD is an abbreviation of RAS-to-CAS Delay) denotes time corresponding to several clocks delayed until a CAS command is received after a reception of a row address strobe (RAS) command. In FIG. 1, tRCD is the time interval from when the external active command ACTIVE is received to when the data read command READ is received. The RAS command is a command to activate a specific page within a memory. Only after the page is activated, a CAS command is received so that data can be input to and/or output from the memory. A page denotes a specific address block within a memory.
FIG. 2 is a timing diagram of signals when a conventional DDR SDRAM is controlled in a CSL controlling approach. Referring to FIG. 2, the conventional DDR SDRAM is designed so that a column selection line signal CSL is controlled in response to rising edges of a clock signal. Both when a CL is 2.5 and when the CL is 3, the column selection line signal CSL is controlled in synchronization with a rising edge 200 of the external clock signal EXCLK. That is, in both cases, the column selection line signal CSL is enabled or disabled at an identical timing.
A first pulse of a first read pulse signal FRP, which is generated to initially read cell data, is produced in synchronization with a rising edge 210, which is one clock behind a rising edge at which a read command READ is received. A second pulse of the first read pulse signal FRP is produced in synchronization with a rising edge 220, which is one clock behind the rising edge 210. Since the pulses of the signal FRP are produced in response to a CSL signal, the timing of the signal FRP when the CL is 2.5 is identical to that when the CL is 3.
On the other hand, the pulses of a second read pulse signal SRP are produced at different timings depending on the value of a CL. When the CL is 2.5, a first pulse of the signal SRP is produced in response to a falling edge 230, which is one clock and a half after the receipt of the read command READ, and a second pulse is produced in response to a falling edge 240, which is one clock after the clock falling edge 230. When the CL is 3, a first pulse of the signal SRP is produced in response to a rising edge 250, which is 2 clocks after the receipt of the read command READ, and a second pulse is produced in response to a rising edge of the signal EXTCLK which is one clock after the rising edge 250. Consequently, a difference between the pulse timing of the signal SRP where CL=2.5 and that where CL=3 is half a clock.
Since the CSL signal is controlled in response to the clock rising edge 200 both when the CL is 2.5 and when the CL is 3, tAA margins within a memory when the CL is 3 are the same as those when the CL is 2.5. Consequently, the conventional DDR SDRAM is designed so that there is no big difference in a tAA margin controlling way between when the CL is 2.5 and when the CL is 3. That is, there is no difference in the pulse timing of the signal CSL or FRP, which determines a read tAA performance, between when the CL is 2.5 and when the CL is 3. There is only a difference of half a clock between the pulse timing of the signal SRP when the CL is 2.5 and that when the CL is 3. Hence, a difference in tRCD, which is a core parameter, between the two cases of CL=2.5 and CL=3 is hardly expected. A gain that can be obtained when the CL is 3 cannot be considered extremely greater than that when the CL is 2.5. That is, a path along which tRCD is determined when the CL is 2.5 is identical to the path when the CL is 3.
The conventional DDR SDRAM is also designed so that when the CL is 3, a first pulse of the signal SRP and a second pulse of the signal FRP are produced at an identical clock (which is indicated by both reference numerals 220 and 250). However, in the conventional DDR SDRAM designed as describe above, if the waveform of the signal SRP is deformed due to a severe jitter of an internal delay locked loop (DLL), the falling edge of the first pulse of the signal SRP moves into the second pulse of the signal FRP. Thus, the conventional DDR SDRAM may fail to operate.
FIG. 3 is a timing diagram of signals when a DLL of the conventional DDR SDRAM jitters. Referring to FIG. 3, when the CL is 3, the rising edge of a second pulse of the signal FRP is earlier than the falling edge of a first pulse of the signal SRP. In this case, an error may be generated during data reading or the like, resulting in a malfunction of the conventional DDR SDRAM. This problem may be generated when the FRP and SRP signals have insufficient pulse-timing margin, since the signal FRP is controlled in response to the external clock signal EXTCLK and the signal SRP is controlled by the internal DLL. Also, as a semiconductor memory is being developed so as to operate within a high frequency range, the interval between clocks becomes narrow. In this case, a timing margin between pulses of the signals SRP and FRP when CL=3 becomes important.